1. Field of the Invention
The invention relates to flash memories, and more particularly to copy back operations of flash memories.
2. Description of the Related Art
A flash storage device, such as a memory card, stores data for a host. When the host wants to store data, the host sends data to the flash storage device for storage. When the host requires data, the flash storage device retrieves the data stored therein and sends the data to the host. The flash storage device generally comprises a controller and a flash memory, wherein the flash memory is used for data storage and the controller receives access commands from the host and accesses data stored in the flash memory according to the access commands.
When a controller of a flash storage device wants to copy data stored at a first address of a flash memory to a second address of the flash memory, the controller often sends a copy back command to the flash memory. To prevent data from damage, data is ordinarily stored in an error correction code (ECC) format. Referring to FIG. 1, a flowchart of a method 100 for executing a copy back command is shown. The controller first sends a copy back command to the flash memory (step 102). When the flash memory receives the copy back command, the flash memory retrieves a first ECC data from the first address according to the copy back command, and then sends the first ECC data to the controller. The controller then starts to receive the first ECC data from the flash memory (step 106). The controller then decodes the first ECC data and performs error correction to obtain a corrected source data corresponding to the first ECC data (step 108). The controller then encodes a parity according to the corrected source data and then combines the corrected source data with the parity to obtain a second ECC data (step 110). The controller then sends the second ECC data to the flash memory (step 112). After the flash memory receives the second ECC data, the controller sends a program command to the flash memory to direct the flash memory to store the second ECC data to a second address (step 114).
Referring to FIG. 2, a schematic diagram of timing of signals transmitted between a controller and a flash memory for performing copy back operations is shown. During a time period T21, the controller sends a copy back command comprising a first address to the flash memory via an input/output bus. During a time period T22, the flash memory reads the first ECC data from the first address, and a ready/busy signal transmitted between the controller and the flash memory is pulled low while the first ECC data is being read. The flash memory then outputs the first ECC data to the controller via the I/O bus during a time period T23. After the controller generates second ECC data according to the first ECC data, the controller then sends the second ECC data and a second address to the flash memory via the I/O bus during a time period T24. The operations 202 are used for transmitting the second ECC data from the controller to the flash memory. The controller then sends a program command to the flash memory via the I/O bus during a time period T25. During a time period T26, the flash memory stores the second ECC data to the second address, and the ready/busy signal is pulled low while the second ECC data is being stored.
Transmission of the second ECC data from the controller to the flash memory in the operations 202, however, requires a long time period and causes delay to execution of the copy back command. In addition, if the first ECC data output by the flash memory contains no error bits, the first ECC data is identical to the second ECC data send from the controller to the flash memory, and transmission of the second ECC data is redundant. A method for executing copy back commands is therefore required to improve performance of a flash storage device.